Basic input/output systems (BIOS) or microcodes are stored on memory devices such as EEPROMs and used to control microprocessors and logic circuits. Today's flexible system-on-system chip architectures require embedded EEPROMs to make possible easy updates of microcode in system configurations. However, generally, EEPROMs require special multi-polysilicon processes and multi-oxidation steps for thin SiO.sub.2 layers. Many masks are needed which result in longer process turnaround times, lower yields, higher costs, and lower reliability.
Integration of various different semiconductor fabrication processes into one specific process generally is complicated and costly. However, K. Ohsaki, et al., "A Single Poly EEPROM Cell Structure for Use in Standard CMOS Processes," IEEE JOURNAL OF SOLID STATE CIRCUITS, Vol. 29, No. 3, March 1994, describes a single polysilicon EEPROM cell structure that may be implemented in a standard CMOS process. This structure consists of adjacently placed NMOS and PMOS transistors with an electrically isolated common polysilicon gate. The common gate works as a "floating gate" and the structure provides an inversion layer as the "control node (gate)." This EEPROM cell (the "Ohsaki Cell") may be easily integrated with CMOS digital an analog circuits, but suffers from severe practical limitations.
Limitations associated with the Ohsaki Cell are fundamental in nature. One limitation is that it requires a high programming and erase voltage. Another limitation is that it requires a big cell size. Suffering from both of these limitations makes the Ohsaki Cell unacceptable for a simple DRAM fabrication process.
In the conventional single polysilicon EEPROM, a particular problem relates to erase techniques. One way to erase these existing structures forces a 5V level on V.sub.D and V.sub.S and forces a -6V bias on the control gate and substrate. The substrate can tie to -6V or be floating. The erase mechanism that results from this procedure is the result of diode breakdown. Unfortunately, this mechanism causes impact ionization and operates as a hole trap to the floating gate. Thus, the problem with this method is that a negative voltage is necessary and the substrate needs to float or tie to the -6V. In this method, a negative charge pump circuit is required.
There are other approaches to erasing structures such as the Ohsaki Cell. One method uses the same type of mechanism as previously described, but ties the control gate to ground. The substrate is tied to -2V and a very high voltage is forced on the drain and source. This method, unfortunately, produces very poor erase efficiency and results in too high a voltage on the source and drain. The high voltage can cause undesirable stress on the EEPROM.
The third method uses an BVCEO breakdown mechanism which causes impact ionization and a hold trap to form at the floating gate. This method, unfortunately, also has very poor erase efficiency and for many other reasons is much less desirable than the two previously described techniques.
Another limitation of the Ohsaki Cell and similar structures is the need for an N-well to serve as the control gate. This design results in a large EEPROM cell size. With the ever-important design objective of smaller memory circuits, the limitation of requiring a large cell size can seriously affect the usefulness of the single polysilicon flash EEPROM.